library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity simple is
port(
s0, s1, s2 : in std_logic;
in_val1, in_val2 : in integer range 0 to 15;
out_val : out integer range 0 to 31 );
end simple;
architecture calculate of simple is
signal sw : std_logic_vector(2 downto 0);
begin
sw<= s2 & s1 & s0;
process( sw, in_val1, in_val2)
begin
case sw is
when "000" => out_val <= in_val1 + in_val2;
when "001" => out_val <= in_val1 - in_val2;
when "010" => out_val <= in_val1 * in_val2;
when "011" => out_val <= in_val1 / in_val2;
when "100" => out_val <= in_val1 rem in_val2;
when "101" => out_val <= in_val1 and in_val2;
when "110" => out_val <= in_val1 or in_val2;
when others => out_val <= in_val1 xor in_val2;
end case;
end process;
end calculate;
이렇게 만들었는데
Error (10327): VHDL error at SIMPLE.vhd(25): can't determine definition of operator ""and"" -- found 0 possible definitions
라는 에러가 뜹니다.
이하 or xor에서도 동일한 오류가 발생하는데 대체 왜 그런지 모르겠네요...
unsigned 때문인가 싶기도 하고...
